High speed autozeroed, sequentially sampled, differential CMOS comparator cells have been developed, adapted and integrated into monolithic circuit arrays for use as high speed analog to digital converters. Such adaptation and use was proposed by Andrew G. F. Dingwall in an article entitled "Monolithic Expandable 6 Bit 20 MHz CMOS/SOS A/D Converter" appearing in IEEE Solid State Circuits, Vol SC-14, pp. 926-932, Dec. 1979.
While such circuit cells worked very well and represented a breakthrough, the limiting factor and drawback were loading errors attributable to the reference voltage resistor ladder. As explained in the article referenced above, "resistor ladder loading errors are of two types: (1) `transient error` associated with instantaneous ladder loading during a single measurement and (2) long-term `recovery error` associated with errors at a new input level after the ladder has been loaded for a long period by inputs at another level." This major source of loading error has resulted because of the current charging requirements of the large number of parallel level shift capacitors and related comparator stages required to carry out the flash conversion process. For eight bit resolution, 256 parallel comparator stages (cells) would be required. Also, this architecture has required that the input voltage have a very low impedance and be driven by a high slew rate amplifier due to the loading of the input stage.
Thus, a hitherto unsolved need has been for an improved input circuit for a CMOS flash A/D converter cell which overcame the aforementioned limitations and drawbacks.